8085 Microprocessor Architecture, Pin Diagram & Addressing Modes for TU BCA Exams
Author: Bhuban Subedi | Subject: Microprocessor (CACS155) | Semester: Second Semester
In the Tribhuvan University (TU) BCA Second Semester Microprocessor (CACS155) curriculum, the Intel 8085 serves as the classic foundational architecture for understanding how central processing units (CPUs) communicate with memory, decode machine instructions, and handle hardware interrupts.
In the final board examination, 8085 Architecture, the Pin Diagram & ALE demultiplexing, and Addressing Modes appear repeatedly as 10-mark long questions and 5-mark short notes.
In this guide, we will break down the internal block diagram, analyze every single bit of the Flag Register, demystify the multiplexed Address/Data bus, and write basic 8085 assembly programs.
1. Intel 8085 Key Specifications Overview
The 8085 is an 8-bit general-purpose NMOS microprocessor introduced by Intel in 1976.
+---------------------------+------------------------------------------------+
| Technical Feature | Specification Details |
+---------------------------+------------------------------------------------+
| Word Length / Data Bus | 8-bit (can process 1 byte in a single cycle) |
| Address Bus Width | 16-bit (Can directly address 2^16 = 64 KB RAM) |
| Operating Frequency | 3 MHz (Driven by 6 MHz external crystal) |
| Power Supply | Single +5V DC supply |
| Packaging | 40-Pin Dual In-line Package (DIP) |
| Internal Architecture | Accumulator-based ALU architecture |
+---------------------------+------------------------------------------------+
2. Functional Block Architecture of Intel 8085
The internal architecture of the 8085 consists of 5 major functional units:
+-------------------------------------------------------------------------------+
| INTEL 8085 INTERNAL ARCHITECTURE |
| |
| +---------------------+ +---------------------+ +---------------------+ |
| | Interrupt Control | | Serial I/O Control | | 8-bit Internal Bus | |
| | (TRAP, RST 7.5, etc)| | (SID, SOD) | +----------+----------+ |
| +---------------------+ +---------------------+ | |
| | |
| +---------------------+ +---------------------+ | |
| | Accumulator (Reg A) | | Temp Register (TR) | | |
| +----------+----------+ +----------+----------+ | |
| | | | |
| +------------+------------+ | |
| | | |
| v | |
| +-------------------+ | |
| | 8-bit ALU | <--------------------------+ |
| +---------+---------+ | |
| | | |
| v | |
| +-------------------+ | |
| | Flag Register | | |
| +-------------------+ | |
| | |
| +-----------------------------------------------+ | |
| | General Purpose Registers (B, C, D, E, H, L) | <------------+ |
| | Stack Pointer (SP - 16 bit) | | |
| | Program Counter (PC - 16 bit) | | |
| | Incrementer / Decrementer Address Latch | | |
| +-----------------------------------------------+ | |
| | |
| +---------------------+ +------------------------------------+ |
| | Instruction Reg (IR)| | Timing and Control Unit (CLK, ALE, | |
| | Instruction Decoder | | RD', WR', IO/M', S0, S1, RESET) | |
| +---------------------+ +------------------------------------+ |
+-------------------------------------------------------------------------------+
Key Functional Blocks Explained:
- Arithmetic Logic Unit (ALU): Performs 8-bit arithmetic (ADD, SUB, INR, DCR) and logical operations (AND, OR, XOR, CMP). It receives inputs from the Accumulator and Temporary Register.
- Accumulator (Register A): An 8-bit register that is part of the ALU. It stores one of the operands for ALU operations and always holds the final result of the operation.
- General Purpose Registers ($B, C, D, E, H, L$): Six 8-bit registers used by programmers to store temporary data. They can be combined into 16-bit register pairs: BC, DE, and HL (where HL commonly serves as the memory pointer
M). - Program Counter (PC – 16 bits): Always holds the memory address of the next instruction to be fetched and executed. It increments automatically after each byte fetch.
- Stack Pointer (SP – 16 bits): Points to the top memory address of the Stack residing in R/W memory.
3. The 8085 Flag Register Breakdown
The Flag Register contains 5 active flip-flops that report the status of the ALU after every arithmetic or logic operation.
Bit Position: D7 D6 D5 D4 D3 D2 D1 D0
+----+----+----+----+----+----+----+----+
Flag: | S | Z | X | AC | X | P | X | CY |
+----+----+----+----+----+----+----+----+
^ ^ ^ ^ ^
| | | | +-- Carry Flag (CY)
| | | +------------ Parity Flag (P)
| | +---------------------- Auxiliary Carry (AC)
| +-------------------------------- Zero Flag (Z)
+------------------------------------- Sign Flag (S)
(Note: X bits are unassigned / don't care)
| Flag | Meaning | Set Condition (1) |
Reset Condition (0) |
|---|---|---|---|
| S (Sign) | Reports polarity of result | Set if MSB ($D_7$) of result is 1 (Negative). |
Set if $D_7$ is 0 (Positive). |
| Z (Zero) | Reports if result is zero | Set if entire 8-bit result is exactly 00H. |
Set if result is non-zero. |
| AC (Auxiliary Carry) | Used for BCD operations | Set if carry is generated from bit $D_3$ to $D_4$. | No carry across nibble boundary. |
| P (Parity) | Checks parity of 1s | Set if result has Even number of 1s. | Set if result has Odd number of 1s. |
| CY (Carry) | Overflow beyond 8-bit | Set if addition generates a carry or subtraction requires a borrow out of MSB $D_7$. | No carry/borrow generated. |
4. Demultiplexing the Address/Data Bus (The Role of ALE)
To reduce pin count on the 40-pin IC, Intel multiplexed the lower 8-bit address lines with the 8-bit data lines into $AD_0 – AD_7$.
- During the first clock cycle of a machine cycle ($T_1$), $AD_0 – AD_7$ carries the lower-order memory address ($A_0 – A_7$).
- During subsequent cycles ($T_2, T_3$), $AD_0 – AD_7$ carries bidirectional data ($D_0 – D_7$).
How ALE (Address Latch Enable) Works:
The microprocessor sends a positive HIGH pulse on pin ALE during $T_1$. An external 8-bit latch IC (such as IC 74LS373) uses this pulse to latch the lower 8-bit address lines, keeping them stable throughout the rest of the memory read/write operation.
+--------------+
| 8085 CPU |
| |
| AD0-AD7 | === (8 lines) ===+=============> Data Bus (D0-D7)
| | |
| | v
| | +----------+
| ALE | ----------> | 74LS373 | =======> Lower Address Bus (A0-A7)
| | | Latch |
| A8-A15| ================================> Higher Address Bus (A8-A15)
+--------------+
5. Hardware Interrupts in 8085 (Priority & Vectored Addresses)
Intel 8085 provides 5 hardware interrupt pins.
+-----------+-----------------------+-------------------+--------------------+
| Interrupt | Priority (1 = Highest)| Trigger Type | Vectored Address |
+-----------+-----------------------+-------------------+--------------------+
| TRAP | 1 (Non-Maskable) | Level & Edge | 0024 H |
| RST 7.5 | 2 (Maskable) | Rising Edge | 003C H |
| RST 6.5 | 3 (Maskable) | HIGH Level | 0034 H |
| RST 5.5 | 4 (Maskable) | HIGH Level | 002C H |
| INTR | 5 (Lowest, Maskable) | Level Sensitive | Non-vectored |
+-----------+-----------------------+-------------------+--------------------+
6. Intel 8085 Addressing Modes with Examples
Addressing mode defines the method by which the instruction specifies the location of the operand/data.
- Immediate Addressing Mode: Data is specified directly inside the instruction byte.
MVI A, 35H(Load byte 35H into Accumulator)LXI H, 2050H(Load 16-bit address 2050H into HL pair)- Register Addressing Mode: Operands reside inside CPU registers. Fast execution.
MOV B, C(Copy contents of register C into register B)ADD D(Add contents of register D to Accumulator)- Direct Addressing Mode: The 16-bit memory address where data is stored is directly given in the instruction.
LDA 3000H(Load Accumulator with data stored at memory address 3000H)STA 4000H(Store Accumulator contents into memory address 4000H)- Indirect (Register Indirect) Addressing Mode: The memory address of the operand is held inside a register pair (usually HL).
MOV A, M(Copy data from memory location pointed to by HL into Accumulator)ADD M(Add data from memory pointed to by HL to Accumulator)- Implied / Implicit Addressing Mode: Operand is implicitly defined within the opcode itself; no operand is specified in syntax.
CMA(Complement Accumulator)RAL(Rotate Accumulator Left through Carry)
7. Solved TU Assembly Program: Adding Two 8-bit Numbers
Problem:
“Write an 8085 assembly language program to add two 8-bit numbers stored at memory locations
2050Hand2051H. Store the 8-bit sum at2052Hand carry at2053H.”
; 8085 Assembly Code
LXI H, 2050H ; Load HL pair with starting address 2050H
MOV A, M ; Move first operand from memory into Accumulator
INX H ; Increment HL pointer to point to 2051H
MOV B, M ; Move second operand into register B
MVI C, 00H ; Initialize register C with 00H to store carry
ADD B ; Add contents of B to Accumulator (A = A + B)
JNC SKIP_CARRY ; If no carry (CY=0), jump to label SKIP_CARRY
INR C ; If carry generated, increment register C
SKIP_CARRY:
INX H ; Increment HL pointer to 2052H
MOV M, A ; Store 8-bit sum at 2052H
INX H ; Increment HL pointer to 2053H
MOV M, C ; Store carry at 2053H
HLT ; Halt microprocessor execution
Summary for TU BCA Exam Preparation
- Accumulator is the central register for all ALU math operations.
- Flag Register reflects ALU status across 5 active flags ($S, Z, AC, P, CY$).
- ALE goes HIGH during $T_1$ to demultiplex $AD_0-AD_7$ using latch IC 74LS373.
- TRAP is the highest priority, non-maskable hardware interrupt.
