Flip-Flops vs Latches Demystified: SR, JK, D, and T Flip-Flop Circuit Diagrams & Truth Tables
Author: Bhuban Subedi | Subject: Digital Logic (CACS105) | Semester: First Semester
In the study of digital electronics and computer architecture, circuits are fundamentally divided into two major families: Combinational Circuits (where output depends solely on current inputs, like Adders and Multiplexers) and Sequential Circuits (which possess memory and where output depends on both current inputs and previous history).
The fundamental building block of all computer memory—from CPU registers and Cache RAM to counters and shift registers—is the Flip-Flop.
In the Tribhuvan University (TU) BCA First Semester Digital Logic examination, questions asking to differentiate between Latches and Flip-Flops, explain the JK Flip-Flop Race-Around Condition, or derive Excitation Tables appear consistently. Let’s break down all four major flip-flops with precision.
1. Latches vs. Flip-Flops: The Core Distinction
Students often use the terms “latch” and “flip-flop” interchangeably. While both are bistable multivibrators capable of storing 1 bit of binary information, their triggering mechanism is fundamentally different.
+------------------------------------+------------------------------------+
| Latches | Flip-Flops |
+------------------------------------+------------------------------------+
| **Level-Triggered:** Output changes| **Edge-Triggered:** Output changes |
| continuously as long as the Enable | only during a clock transition |
| (EN) signal remains HIGH or LOW. | (Positive/Rising or Negative/Falling).|
+------------------------------------+------------------------------------+
| Susceptible to glitches and races | Immune to input noise during clock |
| during the active level. | steady states; highly stable. |
+------------------------------------+------------------------------------+
| Asynchronous control (mostly). | Synchronous control (clocked). |
+------------------------------------+------------------------------------+
| Simpler hardware, faster. | More complex (two latches in cascade).|
+------------------------------------+------------------------------------+
Triggering Visual:
Clock Pulse: _____|‾‾‾‾‾|_____
^ ^ ^
| | +-- Falling Edge (Negative Edge Triggered)
| +-------- HIGH Level (Level Triggered Latch)
+--------------- Rising Edge (Positive Edge Triggered)
2. The 4 Fundamental Flip-Flop Types
1. SR (Set-Reset) Flip-Flop
The SR flip-flop has two primary inputs: $S$ (Set) and $R$ (Reset).
- $S=1, R=0$: Forces output $Q_{n+1} = 1$ (Set state).
- $S=0, R=1$: Forces output $Q_{n+1} = 0$ (Reset state).
- $S=0, R=0$: Maintains previous state ($Q_n$).
- $S=1, R=1$: Forbidden / Invalid State (Forces both $Q$ and $Q’$ to $0$ simultaneously, violating complement rules).
Truth Table:
+---+---+-------+-----------------------+
| S | R | Q | Next State Q(n+1) | State Description |
+---+---+-------+-----------------------+
| 0 | 0 | Qn | Qn | No Change / Memory |
| 0 | 1 | X | 0 | Reset State |
| 1 | 0 | X | 1 | Set State |
| 1 | 1 | X | Undefined / Invalid | Race / Forbidden |
+---+---+-------+-----------------------+
Characteristic Equation:
$$Q_{n+1} = S + R’Q_n \quad (\text{with condition } S \cdot R = 0)$$
2. JK Flip-Flop (The Universal Flip-Flop)
The JK flip-flop was designed to eliminate the invalid ($1, 1$) condition of the SR flip-flop by adding internal feedback from the outputs.
- When $J=1$ and $K=1$, the output toggles (inverts: $0 \rightarrow 1$ or $1 \rightarrow 0$).
Truth Table:
+---+---+-------+-----------------------+
| J | K | Q | Next State Q(n+1) | State Description |
+---+---+-------+-----------------------+
| 0 | 0 | Qn | Qn | No Change (Memory) |
| 0 | 1 | X | 0 | Reset State |
| 1 | 0 | X | 1 | Set State |
| 1 | 1 | Qn | Qn' (Toggle) | Toggle State |
+---+---+-------+-----------------------+
Characteristic Equation:
$$Q_{n+1} = JQ_n’ + K’Q_n$$
3. D (Data / Delay) Flip-Flop
The D flip-flop guarantees that the output follows whatever binary bit is present at input $D$ during the active clock edge. It is constructed by connecting $S = D$ and $R = D’$ using an inverter.
Truth Table:
+---+-------+-----------------------+
| D | Clock | Next State Q(n+1) |
+---+-------+-----------------------+
| 0 | ↑ | 0 |
| 1 | ↑ | 1 |
+---+-------+-----------------------+
Characteristic Equation:
$$Q_{n+1} = D$$
4. T (Toggle) Flip-Flop
The T flip-flop is created from a JK flip-flop by tying both inputs together ($J = K = T$).
– If $T = 0$, output stays unchanged ($Q_{n+1} = Q_n$).
– If $T = 1$, output inverts on every clock edge ($Q_{n+1} = Q_n’$).
Characteristic Equation:
$$Q_{n+1} = T \oplus Q_n = TQ_n’ + T’Q_n$$
3. The Race-Around Condition & Master-Slave JK Solution
What is the Race-Around Condition?
In a level-triggered JK flip-flop, when $J=1$, $K=1$, and the clock pulse width ($t_p$) is greater than the propagation delay of the flip-flop ($t_{pd}$), the output will toggle repeatedly between $0$ and $1$ for the entire duration of the clock pulse. At the end of the pulse, the final state of $Q$ is indeterminate and unpredictable.
$$\text{Condition for Race-Around: } t_p > t_{pd}$$
Clock: |‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|
Output Q: |‾‾‾|___|‾‾‾|___|‾‾‾|___| (Uncontrolled Oscillation)
The Master-Slave JK Flip-Flop Fix:
To eliminate race-around completely, we connect two JK flip-flops in series:
1. Master Flip-Flop: Triggered on the positive edge (or during HIGH clock level).
2. Slave Flip-Flop: Triggered on the inverted clock (LOW clock level) using a NOT gate.
+-------------+ +-------------+
J -----> | | --- Y -----> | | -----> Q
| MASTER | | SLAVE |
K -----> | | --- Y' ----> | | -----> Q'
+-------------+ +-------------+
^ ^
| |
CLK ------------+----------- [NOT Gate] -----+
- During the positive clock, the Master accepts inputs and updates intermediate output $Y$, while the Slave is disabled.
- During the negative clock, the Master is disabled, and the Slave copies $Y$ to the final output $Q$.
- Since output $Q$ only changes when the Master is disabled, feedback cannot trigger multiple toggles in a single cycle!
4. Excitation Tables (Crucial for Counter Design)
In TU BCA exams, when asked to design synchronous counters (e.g., Mod-8 or 3-bit UP Counter), you must use Excitation Tables, which answer: “What inputs are required to transition from present state $Q_n$ to next state $Q_{n+1}$?”
+------------+--------------+---------+---------+-------+-------+
| Present Qn | Next Q(n+1) | S R | J K | D | T |
+------------+--------------+---------+---------+-------+-------+
| 0 | 0 | 0 X | 0 X | 0 | 0 |
| 0 | 1 | 1 0 | 1 X | 1 | 1 |
| 1 | 0 | 0 1 | X 1 | 0 | 1 |
| 1 | 1 | X 0 | X 0 | 1 | 0 |
+------------+--------------+---------+---------+-------+-------+
Summary & TU Exam Key Points
- Latches are level-sensitive; Flip-Flops are edge-sensitive.
- SR has an invalid state ($S=1, R=1$); JK fixes it by toggling.
- Master-Slave configuration eliminates the Race-Around condition by splitting data capture and data output across two distinct clock phases.
- D Flip-Flop is ideal for data storage and registers; T Flip-Flop is ideal for frequency division and counters.
